Solid-state transducer devices with optically-transmissive carrier substrates and related systems, methods, and devices

ABSTRACT

Semiconductor device assemblies having solid-state transducer (SST) devices and associated semiconductor devices, systems, and are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a support substrate, a transfer structure, and a plurality semiconductor structures between the support substrate and the transfer structure. The method further includes removing the support substrate to expose an active surface of the individual semiconductor structures and a trench between the individual semiconductor structures. The semiconductor structures can be attached to a carrier substrate that is optically transmissive such that the active surface can emit and/or receive the light through the carrier substrate. The individual semiconductor structures can then be processed on the carrier substrate with the support substrate removed. In some embodiments, the individual semiconductor structures are singulated from the semiconductor device assembly and include a section of the carrier substrate attached to each of the individual semiconductor structures.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.15/729,487, filed Oct. 10, 2017; which is a continuation of U.S.application Ser. No. 14/706,827, filed May 7, 2015, now U.S. Pat. No.9,812,606; which is a divisional of U.S. application Ser. No.13/747,182, filed Jan. 22, 2013, now U.S. Pat. No. 9,054,235; each ofwhich is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present technology relates to solid-state transducer devices thatemit and/or receive light and substrates for manufacturing such devices.

BACKGROUND

Mobile phones, personal digital assistants (“PDAs”), digital cameras,MP3 players, and other portable electronic devices utilizelight-emitting diodes (“LEDs”), organic light-emitting diodes (“OLEDs”),polymer light-emitting diodes (“PLEDs”), and other solid-statetransducer (“SST”) devices for, e.g., backlighting. SST devices are alsoused for signage, indoor lighting, outdoor lighting, and other types ofgeneral illumination. FIG. 1A is a cross-sectional view of aconventional SST device 10 that includes a support substrate 20 carryingan LED structure 11 having an active region 14 between P-type and N-typesemiconductor materials 15 and 16, respectively. The SST device 10 alsoincludes a first contact 17 and a second contact 19 spaced laterallyapart from the first contact 17. The first contact 17 typically includesa transparent and conductive material (e.g., indium tin oxide (“ITO”))through which light is emitted from the LED structure 11.

To simplify assembly on a substrate (e.g., a printed circuit board(“PCB”)), an SST device can be configured as a “direct-attach” device.FIG. 1B shows a direct-attach SST device 22 coupled to a PCB 24 via thefirst and second contacts 17 and 19. In the direct-attach configuration,the first and second contacts 17 and 19 are bonded to correspondingcontacts 26 and 28 at the PCB 24 (e.g., with a reflowed solderconnection) to electrically and mechanically connect the SST device 22to the PCB 24. As illustrated, the support substrate 20 (FIG. 1A) isomitted from the SST device 22 such that light can escape from an activesurface 30 of the LED structure 11 that is opposite the first and secondcontacts 17 and 19. As such, the first and second contacts 17 and 19 canbe manufactured from opaque materials (rather than transparentmaterials). Although simplifying assembly with the PCB 24, thedirect-attach SST device 22 is challenging to manufacture because thedevice materials and structures are fragile and thus difficult to handleduring manufacturing. For example, the LED structure 11 is thin andwithout the support substrate (e.g., a support wafer) the LED structure11 is prone to warping and damage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are partially schematic cross-sectional diagrams of SSTdevices in accordance with the prior art.

FIGS. 2A-2F are cross-sectional views illustrating a method of forming asemiconductor device assembly in accordance with selected embodiments ofthe present technology.

FIGS. 3A-3C are partially exploded, isometric views of variousoptically-transmissive carrier substrates that can be incorporated intoa semiconductor device assembly in accordance with selected embodimentsof the present technology.

FIGS. 4A-4C are cross-sectional views illustrating singulation ofsemiconductor devices from a semiconductor device assembly having anoptically-transmissive carrier substrate in accordance with selectedembodiments of the present technology.

FIG. 5 is a cross-sectional view of an SST structure incorporating anoptically-transmissive carrier substrate in accordance with selectedembodiments of the present technology.

FIG. 6 is a schematic view of a system that includes a semiconductordevice configured in accordance with selected embodiments of the presenttechnology.

DETAILED DESCRIPTION

Specific details of several embodiments of semiconductor devices havingoptically-transmissive carrier substrates and associated systems andmethods are described below. The term “semiconductor device” generallyrefers to a solid-state device that includes semiconductor material.Although described herein in the context of SST devices, embodiments ofthe present technology can also include other types of semiconductordevices, such as logic devices, memory devices, and diodes, amongothers. Further, the term “semiconductor device” can refer to a finisheddevice or to an assembly or other structure at various stages ofprocessing before becoming a finished device. The term “SST” generallyrefers to solid-state transducers that include a semiconductor materialas the active medium to convert electrical energy into electromagneticradiation in the visible, ultraviolet, infrared, and/or other spectra.For example, SSTs include solid-state light emitters (e.g., LEDs, laserdiodes, etc.) and/or other sources of emission other than electricalfilaments, plasmas, or gases. SSTs can also include solid-state devicesthat convert electromagnetic radiation into electricity.

Depending upon the context in which it is used, the term “substrate” canrefer to a wafer-level substrate or to a singulated, die-levelsubstrate. A person having ordinary skill in the relevant art willrecognize that suitable steps of the methods described herein can beperformed at the wafer level or at the die level. Furthermore, unlessthe context indicates otherwise, structures disclosed herein can beformed using conventional semiconductor-manufacturing techniques.Materials can be deposited, for example, using chemical vapordeposition, physical vapor deposition, atomic layer deposition, spincoating, and/or other suitable techniques. Similarly, materials can beremoved, for example, using plasma etching, wet etching,chemical-mechanical planarization, or other suitable techniques. Aperson having ordinary skill in the relevant art will also understandthat the present technology may have additional embodiments, and thatthe present technology may be practiced without several of the detailsof the embodiments described herein with reference to FIGS. 2A-6. Forease of reference, throughout this disclosure identical referencenumbers are used to identify similar or analogous components orfeatures, but the use of the same reference number does not imply thatthe parts should be construed to be identical. Indeed, in many examplesdescribed herein, identically-numbered parts are distinct in structureand/or function. Furthermore, the same shading may be used to indicatematerials in cross section that can be compositionally similar, but theuse of the same shading does not imply that the materials should beconstrued to be identical.

FIGS. 2A-2F are cross-sectional views of a semiconductor device assembly100 in various stages of manufacture in accordance with selectedembodiments of the present technology. FIG. 2A shows the semiconductordevice assembly 100 after a semiconductor structure 104 has been formedon a support substrate 108 and a conductive material 102 has been formedon the semiconductor structure 104. At this stage, the semiconductordevice assembly 100 also has a mask 106 on the conductive material 102.The mask 106 (e.g., a photoresist mask, a hard mask, or other suitablemask) has apertures that can be used in combination with an etch orother suitable material removal process to form openings 110 in theconductive material 102. As shown, the openings 110 expose surfaces 112of the semiconductor structure 104. The openings 110 also definelocations of individual semiconductor devices 114 in the semiconductordevice assembly 100. As described in further detail below, theindividual semiconductor devices 114 have an active surface 113 throughwhich light is emitted and/or received during operation.

The conductive material 102 can include, for example, a metallicmaterial, a doped semiconductor material, a combination of suchmaterials, or other suitable conductive materials. The semiconductorstructure 104 can include, for example, a single semiconductor materialor a stack of different semiconductor materials. The support substrate108 can be used to form the semiconductor structure 104 and theconductive material 102. For example, the support substrate 108 caninclude an engineered (handle) substrate of poly aluminum nitride,silicon carbine, or other suitable materials for epitaxial growth ofsemiconductor materials. Although omitted for purposes of clarity, thesemiconductor device assembly 100 can include other materials orfeatures. In one embodiment, the semiconductor device assembly 100 caninclude a through-substrate interconnect (not shown) that extendsthrough the semiconductor structure 104 between the conductive material102 and the support substrate 108. In this configuration, thethrough-substrate interconnect can provide an electrical connection witha transparent electrical (e.g., an indium tin oxide (ITO) electrode; notshown) at the active surface 113 of the individual semiconductor devices114.

FIG. 2B shows the semiconductor device assembly 100 after forming firsttrenches 116 that extend through the conductive material 102 and intothe semiconductor structure 104. An etch or other material removalprocess can form the first trenches 116 aligned with the openings 110 inthe conductive material 102. As shown, the first trenches 116 defineindividual mesas 118 that include a portion of the conductive material102 and a portion of the semiconductor structure 104 that are bothseparated from other mesas 118 of the semiconductor device assembly 100.The individual mesas 118 also include first sidewalls 120 that extendbetween exposed surfaces 122 of the support substrate 108 and contactsurfaces 124 of the conductive material 102. In some embodiments, themask 106 (FIG. 2A) can be used to define the locations of the firsttrenches 116. In other embodiments, the mask 106 can be removed beforeforming the first trenches 116. For example, a different mask can beused to form the first trenches 116 or the conductive material 102itself can be used as a mask.

FIG. 2B also shows openings 126 formed in the conductive material 102 ofthe semiconductor device assembly 100. The openings 126 define contacts128 (identified individually as first and second contacts 128 a and 128b) on the semiconductor structure 104. In some embodiments, the openings110 and 126 in the conductive material 102 can be formed (e.g.,patterned and etched) simultaneously. For example, the openings 110 and126 can be formed in a first stage, and the first trenches 116 can beformed in a second stage in which the openings 126 are covered by a maskand the openings 110 are not covered by a mask.

FIG. 2C shows the semiconductor device assembly 100 after a transferstructure 130 is attached to the conductive material 102 of theindividual semiconductor devices 114. The transfer structure 130 caninclude an adhesive (not shown) for at least temporarily binding theindividual semiconductor devices 114 to the transfer structure 130. Inparticular, a temporary transfer substrate 130 is configured to beremovable at a later processing stage without damaging the semiconductordevices 114. For example, the transfer structure 130 can include adie-attach tape. Additionally or alternatively, the transfer structure130 can be removed by a solvent that dissolves the adhesive material ofthe transfer structure 130. Removal of a temporary transfer structure130 is illustrated, for example, in FIGS. 3A-3C. In general, thetransfer structure 130 does not substantially degrade in acidic and/orbasic solutions within a certain pH range. For example, the transferstructure 130 is configured such that it does not substantially degradein the chemical etchant described below with reference to FIG. 2D.

FIG. 2D shows the semiconductor device assembly 100 with the supportsubstrate 108 removed from active surfaces 113 (e.g., light-emittingsurfaces) of the individual semiconductor devices 114. In someembodiments, the semiconductor device assembly 100 can be placed into abath of chemical etchant such that the etchant (drawn as arrows “E” inFIG. 2D) removes material from the interface between the supportsubstrate 108 and the active surfaces 113 of the individualsemiconductor devices 114. When the etchant sufficiently undercuts thesupport substrate 108 below the semiconductor structure 104, the supportsubstrate 108 is released from the semiconductor device assembly 100. Asshown, the etchant can access each side of the individual semiconductordevices 114 via the first trenches 116 between the individualsemiconductor devices 114. Once released, the support substrate 108 canbe recycled and used to form other semiconductor materials and devices.Alternatively, the support substrate 108 can be discarded depending onthe life-cycle of the support substrate 108. For example, the supportsubstrate 108 can be discarded if it has become too thin, contaminated,and/or cycled more than a pre-determined number of times. In otherembodiments, the support substrate 108 can be removed by an alternativeprocess, such as by backgrinding, etching, or chemical and mechanicalpolishing (e.g., CMP).

FIG. 2E shows the semiconductor device assembly 100 after roughening theactive surfaces 113 of the individual semiconductor devices 114. Forexample, the semiconductor structure 104 can be placed in a differentbath of chemical etchant that isotropically removes material from theactive surface 113. In some embodiments, the roughed active surface 113can improve light emission efficiency of the individual semiconductordevices 114 by reducing internal reflection. In addition oralternatively, the roughened active surface 113 can promote adhesion ofother materials and structures with the semiconductor structure 104 ofthe individual semiconductor devices 114. In other embodiments, theactive surfaces 113 are not roughened and accordingly the stage shown inFIG. 2E can be omitted.

FIG. 2F shows the semiconductor device assembly 100 after attaching acarrier substrate 134 to the semiconductor structure 104 of theindividual semiconductor devices 114. The carrier substrate 134 includesa material that is optically transmissive such that the active surfacesof the individual semiconductor devices 114 can emit and/or receive thelight through the carrier substrate 134. For example, the carriersubstrate 134 can be substantially transparent or substantiallytranslucent to light in the visible spectrum (e.g., from about 390 nm toabout 750 nm). The carrier substrate 134 can include, for example, aflexible polymeric material, a glass material (e.g., silicon dioxide orsapphire), a combination of optically transmissive materials, or othersuitable materials. In one embodiment, the carrier substrate 134includes a glass material having a reflective coating.

As illustrated in FIG. 2F, an intermediary material 136 can attach thecarrier substrate 134 to the active surfaces 113 of the individualsemiconductor devices 114. The intermediary material 136 can include,for example, an adhesive, epoxy, or other suitable bonding material. Theintermediary material 136 can be selectively deposited on the activesurface such that it does not substantially interfere with thetransmission of light through the carrier substrate 134. For example, anadhesive can be screen printed at the periphery of the active surfaces113 of the individual semiconductor devices 114. The intermediarymaterial 136 can be substantially transparent, or in other embodimentsthe intermediary material 136 can include a material that alters thelight (e.g., a phosphor). In such cases, the intermediary material canbe dispensed directly on the active surface 113 of the individualsemiconductor devices 114 and/or a first surface 138 of the carriersubstrate 134. For example, a bead of adhesive can be deposited or theadhesive can be screen printed.

Alternatively, the carrier substrate 134 can be bonded by fusing thecarrier substrate 134 with the active surfaces 113 of the individualsemiconductor devices 114. For example, the carrier substrate 134 caninclude a glass material that is fused with a native oxide or adeposited oxide of the semiconductor structure 104 of the individualsemiconductor devices 114. As such, the intermediary material 136 can beeliminated or defined by a region of chemical bonding between the activesurfaces 113 of the individual semiconductor devices 114 and the outersurface 138 of the carrier substrate 134.

In some embodiments, the transfer structure 130 can be removed from thecontacts 128 of the individual semiconductor devices 114 beforecontinuing to other processing stages. Alternatively, the transferstructure 130 can remain on the contacts 128 during subsequentprocessing stages. For example, the transfer structure 130 can shieldthe contacts 128 from contamination and debris associated with operatorhandling, device singulation, or laser scribing. The transfer structure130 can also provide a diffusion barrier that mitigates oxidation of thecontacts 128 of the individual semiconductor devices 114.

In accordance with various embodiments of the present technology, thecarrier substrate 134 provides mechanical support for carrying andprotecting individual semiconductor devices. In particular, the carriersubstrate 134 can be suited for direct-attach manufacturing techniques.For example, semiconductor devices incorporating the carrier substrate(e.g., after die singulation) can have contacts that are suited fordirect bonding, such as eutectic bonding to a printed circuit board(PCB) or other suitable substrate. As discussed above, direct attachdevices can be fragile and difficult to handle during manufacturing.Conventional techniques to improve the strength of direct-attach devicesinvolve the use of thick metal for the electrical contacts to supportthe thin semiconductor devices. However, metal deposition processes forforming the thick metal can be time intensive and expensive. Also, thickmetal can produce large aspect ratios between individual electricalcontacts. Further, in some instances the thick metal can exceed 100 μmin thickness to provide sufficient support, whereas the semiconductormaterials can be less than 10 μm in thickness. This disparity inthickness can cause fracturing of the thinner semiconductor materialduring die singulation. Accordingly, in various embodiments theconductive material 102 and corresponding electrical contacts 128 formedtherein can be thinner than the contacts of conventional direct-attachdevices.

FIGS. 3A-3C show differently shaped carrier substrates 134 (identifiedindividually as wafer-shaped, square-shaped, and rectangular-shapedcarriers substrates 134 a-134 c, respectively). FIGS. 3A-3C also showsthe transfer structure 130 being removed from the carrier substrates 134to expose the contact surfaces 124 of the individual semiconductordevices 114. Referring first to FIG. 3A, the wafer-shaped carriersubstrate 134 a can be sized and shaped for compatibility withdown-stream manufacturing equipment. For example, a vacuum wand, achuck, and/or other mechanical component of a semiconductor processingtool can receive the wafer-shaped substrate 134 a for further processingof the individual semiconductor devices 114. FIG. 3B shows thesquare-shaped carrier substrate 134 b (e.g., a plate of square glass, aplate of polymeric material, or a plate of other suitable materials).Because the square-shaped carrier substrate 134 b is not circular, itmay be less complicated to manufacture than the wafer-shaped carriersubstrate 134 a of FIG. 3A. FIG. 3C shows the rectangular-shaped carriersubstrate 134 c. In this configuration, the carrier substrate 134 ccarries individual semiconductor devices 114 transferred from multipletransfer structures 130. Accordingly, it is expected that such aconfiguration can provide a higher throughput relative to thewafer-shaped and square-shaped carrier substrates 134 a and 134 b ofFIGS. 3A and 3B, respectively. In these and other embodiments, thecarrier substrate 134 can have other configurations that facilitatefurther processing stages of the individual semiconductor devices 114.Such processing stages can include electrical testing of the individualsemiconductor devices 114 on the carrier substrate 134 and/orsingulation of the individual semiconductor devices from thesemiconductor substrate assembly 100. In certain non-illustratedembodiments, processing stages can also forming a transparent electrode(e.g., an ITO electrode) at the active surface 113 of the individualsemiconductor devices 114.

FIGS. 4A-4C are cross-sectional views of the semiconductor deviceassembly 100 in various stages of device singulation. Each of theprocessing stages of FIG. 4A-4C may occur, for example, after theprocessing stage of FIG. 2F. FIG. 4A shows the semiconductor deviceassembly 100 after forming second trenches 140 in the carrier substrate134 to singulate the individual semiconductor devices 114 from thesemiconductor device assembly 100. The second trenches 140 form separatesections 142 of the carrier substrate 134 that remain attached to thesemiconductor structure 104 of the individual semiconductor devices 114.The second trenches 140 can be formed by a variety of mechanicalsingulation techniques, including blade cutting, wafer sawing, or laserablation, among others. Device singulation can also include othersuitable techniques, such as chemically etching the second trenches 140in the carrier substrate 134.

In some embodiments, mechanical singulation includes forming the secondtrenches 140 through a first surface 138 of the carrier substrate 134.In certain instances, however, mechanical singulation techniques cancreate topographical artifacts at the first side walls 120 of the firsttrenches 116 (not shown in FIG. 4A). For example, mechanical singulationcan create indentations (e.g., from blade or saw marks) at the firstside walls 120 of the first trenches 116 (not shown in FIG. 4A). In someof these instances, the topographical artifacts may not have asignificant (or any) impact on the operating performance of theindividual semiconductor devices 114. In other embodiments, the carriersubstrate 134 can be singulated through a second surface 144 of thecarrier substrate 134 that is opposite the first surface 138 and suchthat the second trenches 140 are substantially aligned (e.g., generallyin parallel) with the first trenches 116. As shown in FIG. 4A, secondsidewalls 146 in the second trenches 140 are often relatively rougherthan the first sidewalls 120 of the first trenches 116. The firstsidewalls 120 of the individual semiconductor devices 114 can besmoother than the second sidewalls 146 of the second trenches 140because the first sidewalls 120 can be formed chemically (e.g., an etch)as opposed to mechanically.

Similar to FIG. 4A, FIGS. 4B and 4C show the semiconductor deviceassembly 100 after forming second trenches 140 in the carrier substrate134. FIGS. 4B and 4C are different than FIG. 4A in that the individualmesas 118 of the individual semiconductor devices 114 have a firstplanform shape P₁ that is different planform shape than the carriersubstrate 134. Referring first to FIG. 4B, sections 242 of the carriersubstrate 134 have a second planform shape P₂ that is larger than thefirst planform shape P₁ of the individual mesas 118. In such aconfiguration, a portion of the carrier substrate 134 extends laterallybeyond the first sidewalls 136 of the individual semiconductor devices114. FIG. 4C shows sections 342 of the carrier substrate 134 having athird planform shape P₃ that is larger than the first planform shape P₁of the individual mesas 118. In such a configuration, a portion of theindividual mesas 118 extends laterally beyond the second sidewalls 146of the carrier substrate 134. In general, the planform shapes of theindividual mesas 118 and the carrier substrate 134 can be sizedaccording to the particular configuration of the individualsemiconductor devices 114. For example, the second (larger) planformshape P₂ of the carrier substrate section 242 shown in FIG. 4B caninsure that the carrier substrate 134 completely covers the activesurface 113 of the semiconductor structure 104. In some embodiments,however, the size of planform shapes can be limited by a singulationprocess. For example, the third (smaller) planform shape P₃ of thecarrier substrate section 342 shown in FIG. 4C can be caused by a wafersaw having a blade that is substantially wider than the first trench 116between the individual mesas 118 of the individual semiconductor devices114.

FIG. 5 is a cross-sectional view of the semiconductor device assembly100 having SST structures 414. The individual SST structures 414 includethe conductive material 102 and the semiconductor structure 104, and thesemiconductor structure 104 can include first through thirdsemiconductor materials 104 a-104 c. In some embodiments, the SSTstructure 414 can be configured to emit and/or receive light in thevisible spectrum (e.g., from about 390 nm to about 750 nm) through thecarrier substrate 134. In other embodiments, the SST structure 414 canalso be configured to emit and/or receive light in the infrared spectrum(e.g., from about 1050 nm to about 1550 nm) and/or in other suitablespectra provided that the carrier substrate 134 is opticallytransmissive to such spectra.

In one embodiment, the first semiconductor material 104 a can include anN-type semiconductor (e.g., an N-type gallium nitride (“N-GaN”)) and thethird semiconductor material 104 c can include a P-type semiconductormaterial (e.g., a P-type gallium nitride (“P-GaN”)). In selectedembodiments, the first and third semiconductor materials 104 a and 104 ccan individually include at least one of gallium arsenide (GaAs),aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP),gallium (III) phosphide (GaP), zinc selenide (ZnSe), boron nitride (BN),aluminum gallium nitride (AlGaN), and/or other suitable semiconductormaterials. The second semiconductor material 104 b can define an “activeregion” that includes a single quantum well (“SQW”), MQWs, and/or a bulksemiconductor material. The term “bulk semiconductor material” generallyrefers to a single grain semiconductor material (e.g., InGaN) with athickness between approximately 10 nanometers and approximately 500nanometers. In certain embodiments, the active region can include anInGaN SQW, GaN/InGaN MQWs, and/or an InGaN bulk material. In otherembodiments, the active region can include aluminum gallium indiumphosphide (AlGaInP), aluminum gallium indium nitride (AlGaInN), and/orother suitable materials or configurations.

The SST structure 414 can be formed via metal organic chemical vapordeposition (“MOCVD”), molecular beam epitaxy (“MBE”), liquid phaseepitaxy (“LPE”), hydride vapor phase epitaxy (“HVPE”), and/or othersuitable epitaxial growth techniques. In other embodiments, the SSTstructure 414 can also include other suitable components, such as abuffer material that facilitates the formation of the semiconductorstructure 104 on the support substrate 108 (FIG. 2A). In furtherembodiments, the SST structure 414 can include additional bonding andseed layers to facilitate bonding and/or epitaxial growth.

Once formed, the SST structure 414 can be integrated into an SST device.For example, first and second contacts 428 a and 428 b of the SSTstructure 414 can be directly attached to a printed circuit board orother suitable substrate. Also, other features can be formed on orintegrated into the SST structure, such as a lens over the carriersubstrate 134 of the SST structure 414, an anti-reflective coating or amirror, and/or other suitable mechanical/electrical components (notshown).

The semiconductor device assembly 100 described above with reference toFIGS. 2A-5 can be used to form SST devices, SST structures, and/or othersemiconductor structures that are incorporated into any of a myriad oflarger and/or more complex devices or systems, a representative exampleof which is system 500 shown schematically in FIG. 6. The system 500 caninclude one or more semiconductor/SST devices 510, a driver 520, aprocessor 530, and/or other subsystems or components 540. The resultingsystem 500 can perform any of a wide variety of functions, such asbacklighting, general illumination, power generations, sensors, and/orother suitable functions. Accordingly, representative systems caninclude, without limitation, hand-held devices (e.g., mobile phones,tablets, digital readers, and digital audio players), lasers,photovoltaic cells, remote controls, computers, and appliances.Components of the system 500 may be housed in a single unit ordistributed over multiple, interconnected units (e.g., through acommunications network). The components of the system 500 can alsoinclude local and/or remote memory storage devices, and any of a widevariety of computer readable media.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. Certain aspects of the present technology described in thecontext of particular embodiments may also be combined or eliminated inother embodiments. Additionally, while advantages associated withcertain embodiments of the present technology have been described in thecontext of those embodiments, other embodiments may also exhibit suchadvantages, and not all embodiments need necessarily exhibit suchadvantages to fall within the scope of the technology. Accordingly, thedisclosure and associated technology can encompass other embodiments notexpressly shown or described herein.

I/We claim:
 1. A method of forming a semiconductor device assembly, themethod comprising: forming a conductive material adjacent to asemiconductor structure, the semiconductor structure having an activesurface; forming a trench in the semiconductor structure to form firstand second semiconductor devices; forming openings in the conductivematerial to form electrical contacts for the first and secondsemiconductor devices; forming an intermediate material adjacent to theactive surface; and attaching the first and second semiconductor devicesto a carrier substrate by the intermediate material.
 2. The method ofclaim 1, further comprising removing a transfer structure attached tothe conductive material to expose the electrical contacts.
 3. The methodof claim 1, further comprising: determining a shape of the carriersubstrate based on compatibility with a down-stream manufacturingequipment; and forming the carrier substrate based on the shape.
 4. Themethod of claim 3, wherein the shape corresponds to the semiconductorstructure.
 5. The method of claim 3, wherein the shape includes a wafershape.
 6. The method of claim 3, wherein the shape includes a squareshape.
 7. The method of claim 3, wherein the shape includes arectangular shape.
 8. The method of claim 1, further comprising:determining a size of the carrier substrate based on compatibility witha down-stream manufacturing equipment; and forming the carrier substratebased on the size.
 9. The method of claim 1, wherein forming theintermediate material includes selectively depositing the intermediatematerial on the active surface of the semiconductor structure.
 10. Themethod of claim 1, wherein forming the intermediate material includesprinting an adhesive at a periphery of the active surface of thesemiconductor structure.
 11. The method of claim 1, wherein theintermediate material includes a substantially transparent material. 12.The method of claim 1, wherein the intermediate material includes amaterial capable of altering light passing through the material.
 13. Themethod of claim 12, wherein the material includes a phosphor.
 14. Themethod of claim 1, wherein the intermediate material is defined by aregion of chemical bonding between the active surface and an outersurface of the carrier substrate.
 15. The method of claim 1, wherein thetrench is a first trench, and wherein the method comprises forming asecond trench in the carrier substrate.
 16. The method of claim 15,wherein the second trench is substantially aligned with the firsttrench.
 17. The method of claim 15, wherein a first sidewall of thefirst trench is smoother than a second sidewall of the second trench.18. A method of forming a semiconductor device assembly, the methodcomprising: forming a conductive material adjacent to a semiconductorstructure carried by a support substrate, the semiconductor structurehaving an active surface; forming a trench in the semiconductorstructure to form first and second semiconductor devices; formingopenings in the conductive material to form electrical contacts for thefirst and second semiconductor devices; attaching the first and secondsemiconductor devices to a transfer structure; removing the supportsubstrate, after attaching the first and second semiconductor devices tothe transfer structure; forming an intermediate material adjacent to theactive surface; and attaching the first and second semiconductor devicesto a carrier substrate by the intermediate material.
 19. The method ofclaim 18, further comprising processing the first and secondsemiconductor devices on the carrier substrate.
 20. The method of claim18, further comprising: determining a shape and a size of the carriersubstrate based on compatibility with a down-stream manufacturingequipment; and forming the carrier substrate based on the shape and thesize.